A Compact (m,n) Parallel Counter Circuit Based on Self Timed Threshold Logic

The main result of this paper is the development of a novel, highly compact implementation of the general (m,n)-parallel counter (ie. population counter) based on Self-Timed Threshold Logic (STTL). The presented method is a modification of the Minnick counter. The novel feature of the design is the sharing among all threshold-gates of a single capacitive network for computing the weighted sum of all input bits. Additionally, the differential structure of STTL allows the efficient implementation of the networks of negative weights for layer 1 to layer 2 interconnections. This results in very significant reduction in the number of capacitors and interconnect routing cost and hence total area reduction over other recently reported counter designs. A (7,3) counter is designed using this method. The counter consists of 5 threshold gates arranged in two layers, that is, the resulting circuit has a logic depth of two. Simulation results for the (7,3) counter designed in an industrial 0.25 m process indicate less than 880 W power dissipation operating at 300 MHz.